1. Field of the Invention
The present invention relates to methods and apparatus of producing and polishing a semiconductor device, more particularly relates to methods of producing and polishing a semiconductor device including a step of reducing surface unevenness accompanying the formation of a metal film, and to a polishing apparatus thereof.
2. Description of the Related Art
Along with the increase in integration and reduction of size of semiconductor devices, progress has been made in miniaturization of interconnections, reduction of interconnection pitch, and superposition of interconnections. The importance of the multilayer interconnection technology in the manufacturing process of semiconductor devices is therefore rising.
Aluminum has been frequently used as an interconnection material of a semiconductor device having a multilayer interconnection structure, but in order to reduce the propagation delay of signals in the recent 0.25 μm or less design rule, has been attempted active development of an interconnection process in that aluminum as the interconnection material is replaced by copper. When using copper for interconnections, it is beneficial that both a low resistance and a high electromigration tolerance can be obtained.
In a process using this copper for interconnections, for example, an interconnection process referred to as the damascene process for burying a metal in a groove-like interconnection pattern formed in an interlayer insulation film in advance and removing excess metal film by chemical mechanical (mechno-chemical) polishing (CMP) to form the interconnections has become influential. The damascene process has the features that etching of the interconnections become unnecessary and also a further upper interlayer insulation film becomes flat by itself, so the manufacturing steps can be simplified.
Further, by the dual damascene process, where not only grooves for the interconnections, but also the contact holes are formed as grooves in the interlayer insulation film and where the interconnections and the contact holes are simultaneously buried by the metal, a greater reduction of the interconnection steps can be achieved.
Here, an explanation will be made of an example of the process for forming copper interconnections by the dual damascene process with reference to the accompanying drawings.
First, as shown in FIG. 25A, for example, an interlayer insulation film 302 made of silicon oxide is formed by low pressure chemical vapor deposition (LP-CVD) on a silicon or other semiconductor substrate 301 on which a not illustrated impurity diffusion region is appropriately formed.
Next, as shown in FIG. 25B, contact holes CH communicating with the impurity diffusion region of the semiconductor substrate 301 and grooves M in which it will be formed a predetermined pattern of interconnections to be electrically connected to the impurity diffusion region of the substrate 301 which are formed by using well-known photolithography and etching.
Next, as shown in FIG. 25C, a barrier film 305 is formed on the surface of the interlayer insulation film 302 and in the contact holes CH and the grooves M. This barrier film 305 is formed by a material such as Ta, Ti, TaN, or TiN by well-known sputtering. When the interconnection material is copper and the interlayer insulation film 302 is silicon oxide, since copper has a large diffusion coefficient with respect to silicon oxide, it is easily oxidized. The barrier film 305 is provided to prevent this.
Next, as shown in FIG. 25D, a seed copper film 306 is formed on the barrier film 305 to a predetermined thickness by well-known sputterings.
Then, as shown in FIG. 25E, a copper film 307 is formed so as to bury the contact holes CH and the grooves M by copper. The copper film 307 is formed by the process of plating, CVD, sputtering, etc.
Next, as shown in FIG. 25F, the excess copper film 307 and barrier film 305 on the interlayer insulation film 302 are removed by CMP for flattening.
Due to the above steps, copper interconnections 308 and contacts 309 are formed.
By repeating the above process on the interconnections 308, multilayer interconnections can be formed.
Summarizing the disadvantages to be solved by the invention, in the step of removing the excess copper film 307 by CMP in the copper interconnection forming process using the dual damascene process, because the flattening technique employing conventional CMP involves applying a predetermined pressure between a polishing tool and the copper film for polishing, it suffers from a large damage given to the semiconductor substrate. Especially in a case where an organic insulation film of a small dielectric constant having a low mechanical strength is adopted for the interlayer insulation film, this damage no longer becomes negligible and may cause cracks of the interlayer insulation film and separation of the interlayer insulation film from the semiconductor substrate.
Further, the removal performance differs among the interlayer insulation film 302, the copper film 307, and the barrier film 305, therefore it suffers from the disadvantage that dishing, erosion (thinning), recesses, etc. easily occur in the interconnections 308.
Dishing is a phenomenon where, as shown in FIG. 26, when there is an interconnection 308 having a width of for example about 100 μm at for example a 0.18 μm design rule, the center portion of the interconnection is excessively removed and sinks. If this dishing occurs, the sectional area of the interconnection 308 becomes insufficient. This causes poor interconnection resistance etc. This dishing is apt to occur when copper or aluminum, which is relatively soft, is used as the interconnection material.
Erosion is a phenomenon where, as shown in FIG. 27, a portion having a high pattern density such as where interconnections with a width of 1.0 μm are formed at a density of 50% in a range of for example 3000 μm is excessively removed. When erosion occurs, the sectional area of the interconnections becomes insufficient. This causes poor interconnection resistance etc.
Recess is a phenomenon where, as shown in FIG. 28, the interconnection 308 becomes lower in level at the interface between the interlayer insulation film 302 and the interconnection 308 resulting in a step difference. In this case as well, the sectional area of the interconnection becomes insufficient, causing poor interconnection resistance etc.
Further, in the step of flattening and removing the excess copper film 307 by CMP, it is necessary to efficiently remove the copper film. The amount removed per unit time, that is, the polishing rate, is required to be for example more than 500 nm/mm.
In order to obtain this polishing rate, it is necessary to increase the polishing pressure on the wafer. When the polishing pressure is raised, as shown in FIG. 29, a scratch SC and chemical damage CD are apt to occur in the interconnection surface. In particular, they easily occur in the soft copper. For this reason, it causes opening of the interconnections, short-circuiting, poor interconnection resistance, and other defects. Further, if the polishing pressure is raised, there is the inconvenience that the amount of the scratches, separation of interlayer insulation film, dishing, erosion, and recesses also becomes larger.